1. Field of the Invention
The disclosures herein generally relate to semiconductor devices and methods of manufacturing semiconductor devices, and particularly relate to a semiconductor device and a method of manufacturing a semiconductor device that includes a semiconductor chip, resin for sealing the semiconductor chip, and an interconnection pattern electrically connected to the semiconductor chip.
2. Description of the Related Art
A certain type of conventional semiconductor device includes resin for sealing a semiconductor chip and a multilayer interconnection structure that is formed on the semiconductor chip and the sealing resin to provide interconnection patterns electrically connected to the semiconductor chip. In this configuration, the interconnection patterns serve as external extensions of the interconnections of the semiconductor chip.
In the case of such a semiconductor device, the area size of the semiconductor device in its planar direction may correspond to its footprint on a mother board. Namely, its area size in the planar direction may correspond to the area size of the semiconductor device mounted on the mother board.
FIG. 1 is a cross-sectional view of a related-art semiconductor device.
A semiconductor device 200 illustrated in FIG. 1 includes a semiconductor chip 201, sealing resin 202, a multilayer interconnection structure 203, and external connection terminals 205.
The semiconductor chip 201 includes a semiconductor substrate 208, a semiconductor integrated circuit 209 formed on the semiconductor substrate 208, and electrode pads 211 disposed on and electrically connected to the semiconductor integrated circuit 209. The semiconductor chip 201 has an electrode pad forming surface 201A having the electrode pads 211 formed thereon, a back surface 2018 situated opposite the electrode pad forming surface 201A, and side surfaces 201C. Silicon with a thermal expansion coefficient of 3.5 PPM, for example, may be used as the material of the semiconductor substrate 208.
The semiconductor chip 201 is sealed by the sealing resin 202 such that the electrode pad forming surface 201A and the electrode pads 211 are exposed.
The sealing resin 202 seals the back surface 201B and side surfaces 201C of the semiconductor chip 201. The sealing resin 202 has a multilayer interconnection structure forming surface 202A that is flush with the electrode pad forming surface 201A. Thermosetting epoxy resin, with a thermal expansion coefficient of 8 to 10 PPM, for example, may be used as the sealing resin 202.
The multilayer interconnection structure 203 includes a stacked layer structure 213, external connection pads 214, interconnection patterns 215, and a solder resist layer 217.
The stacked layer structure 213 is made by forming an insulating layer 221 and an insulating layer 222 one after another on the electrode pad forming surface 201A, the electrode pads 211, and the multilayer interconnection structure forming surface 202A.
The external connection pads 214 are disposed on a surface 222A of the insulating layer 222, which surface is situated opposite the surface of the insulating layer 222 that is in contact with the insulating layer 221.
The interconnection patterns 215 are embedded in the stacked layer structure 213. The interconnection patterns 215 are connected to the electrode pads 211 and to the external connection pads 214. With this arrangement, the semiconductor chip 201 is electrically connected to the external connection pads 214.
The solder resist layer 217 is formed on the surface 222A of the insulating layer 222. The solder resist layer 217 has openings 217A that expose the external connection pads 214 at the positions where the external connection terminals 205 are disposed.
The external connection terminals 205 are disposed on the external connection pads 214 exposed through the openings 217A. The external connection terminals 205 serve to electrically connect the semiconductor device 200 to a mounting board (not shown) such as a mother board. Solder balls may be used as the external connection terminals 205 (see U.S. Pat. No. 6,271,469, for example).
In the related-art semiconductor device 200, the sealing resin 202 having a thermal expansion coefficient (e.g., 8 to 10 PPM) different from the thermal expansion coefficient (e.g., 3.5 PPM) of the semiconductor substrate 208 is disposed to surround the side surfaces of the semiconductor substrate 208. With such a structure, the semiconductor device 200 may warp due to a difference in thermal expansion coefficients between the semiconductor substrate 208 and the sealing resin 202.
If the semiconductor device 200 warps, it is not possible to mount the semiconductor device 200 on a mounting board such as a mother board. In other words, the semiconductor device 200 cannot be electrically connected to the mounting board.
In the related-art semiconductor device 200, further, the multilayer interconnection structure 203 is disposed only on the multilayer interconnection structure forming surface 202A of the sealing resin 202. In other words, a multilayer interconnection structure is not formed on the surface 202B of the sealing resin 202 that is situated opposite the multilayer interconnection structure forming surface 202A. This is also a factor that contributes to the fact that the semiconductor device 200 is easy to warp. Further, this configuration may make it difficult to provide the semiconductor device 200 with a further multilayer interconnection structure.
Accordingly, it may be desirable to provide a semiconductor device and a method of manufacturing the semiconductor device that can avoid the warpage of the semiconductor device and that can increase the extent of multilayer interconnection structures.